Design of a 2X2 Reading and Writing Array for Programmable Metallization Cell

Authors

  • Ranga Reddy Kandala Electrical Engineering Department, California State University, Long Beach, CA 90840, USA
  • Dhirender Singh Electrical Engineering Department, California State University, Long Beach, CA 90840, USA
  • Fei Wang Electrical Engineering Department, California State University, Long Beach, CA 90840, USA

Keywords:

Non-volatile Memory, Read circuitry, Write circuitry.

Abstract

A transistor level 2X2 reading and writing array for non-volatile memory cell has been designed. This circuit is an innovative reading and writing circuit designed specifically for Programmable Metallization Cells (PMC). The write circuitry is designed to provide appropriate positive and negative voltage bias to an individual PMC memory cell in order to program it to high resistance state (write '0') or low resistance state (write '1'). A terminal switching mechanism is constructed using two pairs of complimentary MOS transistors in writing circuit.

References

Fei Wang,

M.N. Kozicki, M. Yun, S. J. Yang, J.P Aberouette, J.P. Bird,

M. N. Kozicki, C. Gopalan, M. Balakrishnan, M. Park, M. Mitkova,

I. Chaitanya et al.

F. Wang, W. P. Dunn, M. Jain, C. De Leo, N. Vickers ,

Sakamoto et al.

F. Wang et al.

Dhirender Singh and Fei Wang,

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Published

2016-06-08

How to Cite

Kandala, R. R., Singh, D., & Wang, F. (2016). Design of a 2X2 Reading and Writing Array for Programmable Metallization Cell. International Journal of Sciences: Basic and Applied Research (IJSBAR), 27(3), 89–101. Retrieved from https://www.gssrr.org/index.php/JournalOfBasicAndApplied/article/view/5849

Issue

Vol. 27 No. 3 (2016)

Section

Articles

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